Description

Power, performance and area (PPA) is a significant challenge for designers and architects building any silicon. The problem is three-dimensional and complex to solve with precise certainty. Invariably, heavy use of simulation vectors is exercised to examine the relationship between these dimensions, but the analysis is non-exhaustive leaving room for errors. Verification engineers focus primarily on structural coverage to expose unreachable code in designs, mostly towards the tail end of the projects. 

While structural coverage is useful to expose unreachable (deadcode) code, it cannot expose redundant, partial or under-utilised code.  

footprint™ allows an efficient and fast analysis for identifying redundant design components that provides a quick feedback loop to the architects and designers while they bring up a new design, allowing them to exhaustively analyse the wasted area while focussing on power and performance optimisations. footprint efficiency stems from making the analysis on a component level. The report generated from footprint is a component specific categorization. 

footprint is part of the axiomiser® platform that offers a one-stop shop for all its apps.

Prerequisites

Design available to compile in VHDL/Verilog/SystemVerilog

Ubuntu 20.04 and later

Red Hat Enterprise Linux (RHEL) 8 and later

Debian 12

Cadence Jasper Platform®

Google Chrome®


What are the benefits?

Redundant area exposed

Potential energy saving

Fast turnaround on silicon quality

Driven by automation 

Shrinking time-to-market

Precision not possible with simulation 

Frequently Asked Questions

  • How do I get started?

    Sign up on our portal by creating an account, then [email protected] to request access to the software. We will then enrol you in our software platform and provide you with a license key.

  • Do I need another formal verification tool?

    Yes, you need a model checker from the Cadence Jasper Platform to run footprint.

  • If I wanted to learn more, can I get help?

    We are pioneers in providing custom training and turnkey services on complex projects. You can browse this portal to find more information on our training courses, and email us on [email protected] to get more information on our consulting & services.

  • Can footprint verify a design with multi-clocks and resets?

    Yes.

  • My design has some encrypted RTL blocks. Will footprint still work?

    If your design can be compiled in a formal tool, you can use footprint. Alternatively, you can blackbox the encrypted design blocks.

  • Do you offer an evaluation?

    Yes, please contact us to discuss.