Comprehensive Course in Formal Verification Methodology - GOLD +
Interested in this training. Email us at [email protected] for more information.
Formal verification has a modern history of over 70 years, and yet it is the least understood technology for practical use. Formal methods are used these days to find bugs and sign-off complex hardware designs with over 1.1 billion gates and yet very few people know the secrets of applying it successfully.
This course provides an overview of formal methods covering all essential technologies of formal including theorem proving, property checking, and equivalence checking. The bulk of the course is focused on property checking and how it can be deployed for large-scale verification in the industry. We focus on problem-solving & methodology of problem reduction to tackle the main challenge of formal verification - namely proof convergence and coverage & sign-off.
Designers
Architects
Verification engineers
Passion to learn formal methods
Some knowledge of digital design
Verilog/VHDL/SystemVerilog
Why use formal verification?
History of formal methods
Foundations of formal methods
How to deploy agile formal?
Abstractions
Focus on proof convergence
Bug hunting
Six-dimensional coverage
When to use simulation and when to use formal?
Live demos
Hands-on experience
Lifetime access to the material
Formative Quizzes
Graded Quiz Exam
Certificate
Dr. Ashish Darbari